![]() ![]() After a back porch interval of 1.02 ms, the next frame begins. After this, a front porch interval of 0.45 ms is inserted before the vertical sync signal goes low for 64 μs. The lines are displayed within a 15.25 ms window. In a similar fashion, negative pulses on the vertical sync signal mark the start and end of a frame of video lines and ensure that the monitor displays the lines between the top and bottom edges of the visible monitor screen. The red, green and blue signals are blanked during the 6.6 μs interval comprised of the front porch, sync pulse and back porch. Therefore, a single line of pixels occupies 25.17 μs of a 31.77 μs interval. After a back porch interval of 1.89 μs, the next line of pixels begins. After this, a front porch interval of 0.94 μs is inserted before the horizontal sync signal goes low for 3.77 μs. ![]() The pixels are sent on the RGB signal lines within a 25.17 μs window. Negative pulses on the horizontal sync signal mark the start and end of a line and ensure that the monitor displays the pixels between the left and right edges of the visible screen area. The timing for the VGA sync signals is shown in below. In order to send a frame of pixels to the monitor, two sync signals are required: a horizontal sync to indicate the start and stop of each line of pixels going from left to right on the screen, and a vertical sync that marks the top and bottom lines so they stack up to form an image. VGA frame size is expressed as w x h with typical sizes of 640 x 480, 800 x 600, 1024 x 7 x 1024. This simplifies the DAC circuitry to a single resistor driven by a single output.Īn image (or frame) on a monitor screen is composed of h lines each containing w pixels. This is done by applying the same level to each of the RGB inputs. Replicating the DAC for each analog input gives us a palette of 32 x 32 x 32 = 32768 different colors selectable through fifteen digital control lines.įor many applications we only need two colors: black and white. Signal levels between 0 (completely dark) and 0.7 V (maximum brightness) control the intensity of each color component, which combine to make the final color of a pixel on the monitor screen.Įach analog color input can be set to one of 32 levels by five digital outputs using a simple five-bit digital-to-analog converter (DAC) as shown below. There are three signals - red, green, and blue (RGB) - that send color information to a VGA monitor. (And for all who are about to ask: NO, I do not have a Verilog version of this.) Hopefully you'll find enough comments in the VHDL code to understand how it all relates to what I'll describe below. ![]() ![]() Finally, I'll post an archive of the Xilinx ISE 13 project files that compiles into a downloadable bitstream for the FPGA on the XuLA board. Then I'll show you the block-level architecture of a module for generating VGA video and an application that uses the module to display an image stored in SDRAM. I'll start off with the basics of VGA video signals: signal levels and timing. What I didn't show was the code that lets the FPGA fetch an image from SDRAM and display it on a monitor. In my previous blog post, I showed a circuit I built to interface my XuLA FPGA board to a VGA monitor. ![]()
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